Overlay · hardware and AI research lab
Etched where it's stable, rewritable where it changes: speed and flexibility on one die. Every weight sits on the chip, right beside the compute, so one user's answer streams out as fast as the silicon allows.
For scale: on a B200 we measured up to ~890 tok/s for one user on the same 4B (vLLM, MTP-3, FP8; 4-bit not measured)measured; a tuned engine could be up to ~2× faster aloneest.. Pre-silicon: chip figures are design estimates, and a 28nm test chip is planned. Every number links to its source.
The problem
For a single user, a GPU's speed is capped by how fast it can stream the model's weights in from HBM, step after step. Agents make many short calls, and every one of them waits.
Weights cross from memory into the chip for every step.
Weights already sit beside the compute lanes, so tokens stream out.
Why now
Model-specific chips are real. AMD agreed to acquire Taalas in Aug 2026reported
Single-user speed is being bought. Nvidia licensed Groq's inference technology in Dec 2025reported
Reading and writing are splitting. AWS announced Trainium for prompts with Cerebras for answers in Mar 2026reported
The mixed die
One die, three kinds of memory, all beside the compute. The stable core of a model can be etched into dense mask ROM, the parts that change stay in rewritable SRAM, and each user's memory is always SRAM. That's how we get speed and flexibility at once.
The dense, fixed bulk of a model, in a one-transistor mask ROM at about 2× SRAM's densityest., pending silicon.
The parts that change: updates, customer fine-tunes, adapters and steering. The same chip keeps up with new versions.
One user's KV cache and model state, rewritten every token, so always SRAM.
This is our architecture and direction, not a measured result. Our first chip is all-SRAM: SRAM first, ROM later. The etched core is on our roadmap, and our 28nm test chip puts a one-transistor ROM array beside the SRAM to measure it.
QTile does the split
Our compiler splits a model into its parts, gives each part its own bit-width from measured sensitivity, and places it: etched or rewritable. The placement pass exists and is being measured on real Qwen3.5 models. It isn't a finished product.
Adapting the model to the chip
Updates and fine-tunes are written into the rewritable layer as small add-ons, such as LoRA-style adapters, deletion masks or steering registers. A first test of a small writable layer learned a new tool format as well as LoRA, but took over chat answers; a gated version is in design.
Base-model releases can change much of a model, so how much of a model can be etched is measured per model family. A new base model is not an add-on.
Our approach
We chose the model and sized the chip around it, together. Three decisions make the speed.
Every weight of a 4B model, at 4 bits, in SRAM on one 5nm-class die of ~723.6–754.9 mm² at 8Kest.. It keeps 93% of its IFEval score with no retrainingmeasured.
Our first chip keeps every weight in SRAM, so a same-shape model update is a reload, not a new chip. Small models improve every few months; the die keeps up.
A hybrid model: 24 of its 32 layers keep a fixed-size state and only 8 keep a growing cache, so one user's ~8K tokens of context fit on the dieest..
The token race
An agent asks whether a tool call is safe. Every lane writes the same reasoning, slowed down by the same factor so you can watch.
The answer is illustrative. GPU: the most we measured on a B200 serving one user with standard engines (vLLM, MTP-3, FP8; 4-bit not measured); a tuned engine could be up to ~2× faster alone. Tuned GPU: our estimate that a tuned engine could reach up to ~2× the measured rate. Overlay: a pre-silicon estimate for one user, shown at 15,000 tok/s, the middle of its range; the die is sized for one user's 8K cache.
First
Agent action checks, with thinkingThe 4-bit 4B reasons briefly, then allows or blocks each tool call.
Next
Code generation with a repair roundA write-test-fix step (2,000 tokens in, 1,000 out): 0.18–0.20 s of model time on the chip, against 0.90–1.38 s on a lone B200, or ~0.45–0.69 s tunedest.. With ~2 s of tests a round (tests assumed), ~1.3–1.6× faster end to endest.. At 4 bits it reaches 67.5% on MBPP+, 1 point under its barmeasured.
Then
Longer context, bigger modelsCopies of the die for gpt-oss-120b: ~25–27 dies before the program store, ~5% more afterest.. 1T is a design study.
The pipeline
QTile, our compiler, turns a model into a program for one integer instruction set, then checks the hardware against an exact interpreter, bit for bit.
Six model families today, including Qwen3.5's hybrid layers.
InputEach part of the model goes to int4 or int8 and into on-chip SRAM.
Real-model sensitivity: in progressIn Verilator simulation, every logit matches the exact integer interpreter.
Measured · simulation onlyA 28nm test chip first, then the 5nm-class die.
Planned · back ~mid-2027est.Lab notes
Software and simulation, run on our own harnesses. Nothing here is from silicon yet.
RTL verificationMeasured
In Verilator, 300 of 300 random programs, small models of six families and a trained 1-bit Qwen3.5-0.8B (8 of 8 steps, on two prompts) match the exact integer interpretermeasured. Simulation only: no synthesis or timing yet.
Model qualityMeasured
At 4 bits the 4B keeps 93% of its IFEval score, 91–99% of MMLU and 94% of code with repair, the last 1 point under its pre-registered barmeasured. Thinking off.
Agent safetyMeasured
On InjecAgent, over 26 held-out attacker instructions (830 cases), the 4-bit 4B allows 89.2% of requested calls against an 85% pre-registered bar, at 95.6% balanced accuracy, blocking 4.0% of legitimate callsmeasured. One benchmark; the threshold is set per deployment.
CompilerIn progress
QTile's placement pass maps all 4,205,751,296 parameters of Qwen3.5-4B, part by part, and measures how few bits each part can take, with a public int4 checkpoint as the bar. Runs are in progress.
Roadmap
The plan, with estimated timing. Each step is gated on the one before it.
Bit-exact RTL; 4-bit quality and action checks measured.
The same 4B, served on rented GPUs, for traction.
A 4–7 mm² shared-wafer tape-out, with a ROM array beside the SRAM.
Energy, clock and leakage measured.
Gated on a committed design partner.
Copies of the die for larger models; 1T as a design study.
Contact
Contact: to be added.