Sources for every number
Every number on the Overlay page, with how we know it. Overlay is pre-silicon: there is no chip yet, so every chip figure is a design estimate. Measured results come from software, GPUs and simulation.
Labels
- measured
- we ran it: software, GPU or simulation. Nothing on silicon yet.
- est.
- a design estimate. Every Overlay chip figure is one until silicon.
- reported
- a third party's figure or event, as published.
- plan
- a dated plan or design direction; the dates are estimates.
- design
- our architecture and direction, not a measured result.
- exact
- a count, from a public model config or the page itself.
- derived
- arithmetic on other numbers here.
- in progress
- measurements under way; no result is claimed.
- illustration
- a drawing that shows a mechanism; it carries no data.
Claims
| # | Claim | Section | Label | Source |
|---|---|---|---|---|
| 1 | ~14,000–16,000 tokens/s for one user, on one die | Hero; Problem; Token race | est. | Overlay design estimate |
| 2 | One die holds every weight of a 4B model in SRAM, sized for one user's 8K-token cache | Hero; Approach | est. | Overlay design estimate |
| 3 | A 4B model (~4.2B weights with its head), at 4 bits | Hero; Approach; Token race | exact | Qwen3.5-4B model config, Hugging Face (read Nov 2026) |
| 4 | Pre-silicon; a 28nm test chip is planned | Hero; Pipeline; Roadmap | plan | Overlay plan |
| 5 | The 3D chip is a concept render of the proposed die, not silicon; it claims no dimensions, tile counts or areas | Hero | illustration | Drawing |
| 6 | Serving one user, a GPU's speed is capped by how fast it streams the model's weights from memory | Problem | measured | Overlay measurement, Nov 2026 |
| 7 | ~890 tok/s: the most we measured for one user on a B200, same 4B model (vLLM, MTP-3, FP8; 4-bit not measured) | Hero; Problem; Token race | measured | Overlay measurement, Nov 2026 |
| 8 | ~165–255 tok/s each, for many users on a busy B200, same model (a GPU figure, not Overlay) | Problem | est. | Overlay measurement on an H100, scaled to a B200 (Overlay design estimate) |
| 9 | AMD agreed to acquire Taalas (6 Aug 2026) | Problem | reported | AMD newsroom; AMD Form 10-Q, quarter ended 26 Sep 2026 |
| 10 | Nvidia licensed Groq's inference technology (24 Dec 2025) | Problem | reported | As reported by CNBC, via Digital Citizen and ITdaily |
| 11 | AWS announced Trainium for reading prompts with Cerebras for writing answers (13 Mar 2026); the service is planned | Problem | reported | IEEE ComSoc Technology Blog, 14 Mar 2026 |
| 12 | One 5nm-class die of ~723.6–754.9 mm² at 8K context | Approach | est. | Overlay design estimate |
| 13 | At 4 bits the 4B keeps 93% of its IFEval score, with no retraining | Approach; Lab notes | measured | Overlay measurement, Nov 2026 |
| 14 | A same-shape model update is a reload, not a new chip; small models improve every few months | Approach | design | Overlay plan; for an example of an update on the same architecture, see the Qwen3-4B-Instruct-2507 model card |
| 15 | 24 of the 4B's 32 layers keep a fixed-size state; 8 keep a growing cache | Approach | exact | Qwen3.5-4B model config, Hugging Face (read Nov 2026) |
| 16 | One user's ~8K tokens of context fit on the die | Approach | est. | Overlay design estimate |
| 17 | Token race, GPU lane: 890 tok/s, FP8, untuned; a tuned engine could be ~2× faster | Token race | measured | Overlay measurement, Nov 2026 (the tune: Overlay design estimate) |
| 18 | Token race, Overlay lane: shown at 15,000 tok/s, the middle of ~14,000–16,000 | Token race | derived | Derived from #1 |
| 19 | All lanes are slowed 150× so the race can be watched; the speed ratios are kept | Token race | presentation | Page setting |
| 20 | 41 tokens: the illustrative answer has 41 words, each counted as one token | Token race | exact | Counted on the page |
| 21 | Real-time counters: 41 ÷ 15,000 = 2.7 ms on the chip; 41 ÷ 1,780 = 23.0 ms on a tuned GPU; 41 ÷ 890 = 46.1 ms on the measured GPU | Token race | derived | Derived from #17, #18 and #88 |
| 22 | First use: agent action checks with thinking; next: code generation with a repair round | Token race | plan | Overlay plan |
| 23 | gpt-oss-120b on ~25–27 dies before the program store, ~5% more after | Token race | est. | Overlay design estimate |
| 24 | 1T is a design study, not a product | Token race; Roadmap | est. | Overlay design estimate |
| 25 | The compiler takes six model families today, including Qwen3.5's hybrid layers | Pipeline | exact | Overlay measurement, Nov 2026 |
| 26 | Each part of a model goes to int4 or int8 | Pipeline | exact | Overlay measurement, Nov 2026 |
| 27 | Real-model sensitivity measurements: in progress | Pipeline; Lab notes | in progress | Overlay measurement, Nov 2026 |
| 28 | In Verilator simulation, every logit matches the exact integer interpreter; no synthesis or timing yet | Pipeline; Lab notes | measured | Overlay measurement, Nov 2026 |
| 29 | A 28nm test chip, then the 5nm-class die; test silicon back ~mid-2027 | Pipeline; Roadmap | est. | Overlay plan |
| 30 | 300 of 300 random programs bit-exact in simulation | Lab notes | measured | Overlay measurement, Nov 2026 |
| 31 | Small models of six families bit-exact in simulation | Lab notes | measured | Overlay measurement, Nov 2026 |
| 32 | A trained 1-bit Qwen3.5-0.8B bit-exact on 8 of 8 steps, on two prompts | Lab notes | measured | Overlay measurement, Nov 2026 |
| 33 | The RTL chart (waveform and logits drawn twice) is an illustration | Lab notes | illustration | Drawing |
| 34 | IFEval: 82.8% at full precision, 77.1% at 4 bits | Lab notes | measured | Overlay measurement, Nov 2026 |
| 35 | MBPP+ (code with repair): 71.5% at full precision, 67.5% at 4 bits | Lab notes | measured | Overlay measurement, Nov 2026 |
| 36 | 91–99% of MMLU kept at 4 bits | Lab notes | measured | Overlay measurement, Nov 2026 |
| 37 | 94% of code with repair kept, 1 point under its pre-registered bar | Lab notes | measured | Overlay measurement, Nov 2026 |
| 38 | Quality measured with thinking off | Lab notes | measured | Overlay measurement, Nov 2026 |
| 39 | InjecAgent: 26 held-out attacker instructions, 830 cases | Lab notes | measured | Overlay measurement, Nov 2026 |
| 40 | 89.2% of requested calls allowed against an 85% pre-registered bar; lower bound 83.2% | Lab notes | measured | Overlay measurement, Nov 2026 |
| 41 | 95.6% balanced accuracy | Lab notes | measured | Overlay measurement, Nov 2026 |
| 42 | 4.0% of legitimate calls blocked | Lab notes | measured | Overlay measurement, Nov 2026 |
| 43 | One benchmark; the threshold is set per deployment | Lab notes | measured | Overlay measurement, Nov 2026 |
| 44 | Qwen3.5-4B has 4,205,751,296 parameters | Lab notes | exact | Qwen3.5-4B model config, Hugging Face (read Nov 2026) |
| 45 | Placement chart widths: MLP 2,265.0M, DeltaNet projections 1,010.7M, embedding/head 635.7M, attention 293.7M parameters | Lab notes | exact | Qwen3.5-4B model config, Hugging Face (read Nov 2026), summed by part |
| 46 | A public int4 checkpoint is the quality bar for the placement pass | Lab notes | method | RedHatAI/Qwen3.5-4B-quantized.w4a16, Hugging Face (read Nov 2026) |
| 47 | Now: software and simulation (bit-exact RTL; 4-bit quality and action checks measured) | Roadmap | measured | Overlay measurement, Nov 2026 |
| 48 | 0–3 months: hosted action checks, the same 4B on rented GPUs | Roadmap | plan | Overlay plan |
| 49 | 3–9 months: a 28nm test chip, a 4–7 mm² shared-wafer tape-out, with a ROM array beside the SRAM | Roadmap | plan | Overlay plan |
| 50 | ~mid-2027: test silicon back; energy, clock and leakage measured then | Roadmap | est. | Overlay plan |
| 51 | 9–36 months: the product die, gated on a committed design partner | Roadmap | plan | Overlay plan |
| 52 | Beyond: copies of the die for larger models | Roadmap | plan | Overlay plan |
| 59 | The B200 figure ran at FP8; 4-bit was not measured | Hero; Problem; Token race | measured | Overlay measurement, Nov 2026 |
| 60 | A tuned GPU engine could be up to ~2× faster for one user | Hero; Problem; Token race | est. | Overlay design estimate |
| 61 | The speed is for one user; the die is sized for one user's 8K-token cache | Hero; Approach; Token race | est. | Overlay design estimate |
| 65 | A write-test-fix step (2,000 tokens in, 1,000 out): 0.18–0.20 s of model time on the chip, 0.90–1.38 s on a lone B200 | Token race | est. | Overlay design estimate; GPU side: Overlay measurement on an H100, scaled to a B200 (Overlay design estimate) |
| 66 | The same step on a tuned lone B200: ~0.45–0.69 s | Token race | est. | Derived from #65 and #60 |
| 67 | End to end, with ~2 s of tests a round (assumed): ~1.3–1.6× faster than a lone B200 | Token race | est. | Overlay design estimate; the test time is assumed |
| 68 | 67.5% on MBPP+ at 4 bits, 1 point under its bar | Token race | measured | Overlay measurement, Nov 2026 |
| 71 | Etched where it's stable, rewritable where it changes: speed and flexibility on one die | Hero | design | Overlay plan |
| 72 | The mixed die has three regions: an etched mask-ROM core, rewritable SRAM, and per-user memory (always SRAM) | Mixed die | design | Overlay plan |
| 73 | A one-transistor mask ROM at about 2× SRAM's density, pending silicon | Mixed die | est. | Overlay design estimate |
| 74 | Our first chip is all-SRAM: SRAM first, ROM later; the etched core is on our roadmap | Mixed die; Approach | plan | Overlay plan |
| 75 | The 28nm test chip puts a one-transistor ROM array beside the SRAM | Mixed die; Roadmap | plan | Overlay plan |
| 76 | QTile's placement pass exists, is being measured on real Qwen3.5 models, and isn't a finished product | QTile | in progress | Overlay measurement, Nov 2026 |
| 77 | Part sizes in Qwen3.5-4B: embeddings/head 635.7M, MLP 2,265.0M, attention 293.7M, DeltaNet projections 1,010.7M parameters | QTile | exact | Qwen3.5-4B model config, Hugging Face (read Nov 2026) |
| 78 | The router exists in MoE models only: 21.0M parameters in Qwen3.5-35B-A3B; int8 by default; kept in rewritable SRAM | QTile | exact | Qwen3.5-35B-A3B model config (read Nov 2026); format and placement: Overlay plan |
| 79 | Embeddings stay at int8: the compiler's embedding step reads int8 | QTile | exact | Overlay measurement, Nov 2026 |
| 80 | Each part gets its own bit-width (int4 or int8) from measured sensitivity, part by part | QTile | in progress | Overlay measurement, Nov 2026 |
| 81 | Placement: MLP and attention are etch candidates if they hold across releases; DeltaNet projections stay rewritable; per-user state is always SRAM | QTile | design | Overlay plan |
| 82 | Per-user state: 8-bit cache and bf16 DeltaNet state, measured on Qwen3.5 | QTile | measured | Overlay measurement, Nov 2026 |
| 83 | Updates and fine-tunes go into the rewritable layer as small add-ons: LoRA-style adapters, deletion masks, steering registers | QTile | design | Overlay plan; deletion masks: arXiv 2611.10866 (Nov 2026) |
| 84 | A first test of a small writable layer learned a new tool format as well as LoRA, but took over chat answers; a gated version is in design | QTile | measured | Overlay measurement, Nov 2026 |
| 85 | Base-model releases can change much of a model, so how much can be etched is measured per model family | QTile | measured | Overlay measurement, Nov 2026 (two releases of one large public model) |
| 86 | "Rewritable from day one": our first chip keeps every weight in SRAM, so a same-shape update is a reload | Approach | plan | Overlay plan |
| 87 | The mixed-die and adapting graphics are schematic | Mixed die; QTile | illustration | Drawing |
| 88 | Token race, tuned GPU lane: B200, one user, ~1,780 tok/s, about 2× the measured 890 | Token race | est. | Overlay estimate: a tuned engine could reach up to ~2× the measured rate |
Some numbers are skipped. Preview, Nov 2026.